Lithography and optical proximity correction (OPC) contours cannot accurately predict the hard mask contour of a metal layer (Mx). Lithography and OPC contours also cannot accurately predict the dielectric etch of a via layer (Vx). Therefore, it is difficult to accurately predict the overlap between Mx+1 and Vx layers, e.g., V0, M1, V1, M2, V2, and M3, especially for the back-end-of-line with the self-aligned via in a trench first via last process. FIG. 1 schematically illustrates a background layering of Mx+1 and Vx layers. For example, a Vx layer 101, e.g., V0, may be formed between the contact layer 103 and Mx+1 layer 105, e.g., M1. Next, a Vx+1 layer 107, e.g., V1, may be formed between the Mx+1 layer 105 and the Mx+2 layer 109, e.g., M1 and M2, respectively. Thereafter, a Vx+2 layer 111, e.g., V2, may be formed between the Mx+2 layer 109 and the Mx+3 layer 113, e.g., M2 and M3, respectively.
Currently, there is a gap or bias between the assumed trench CD 201 and the actual trench CD 203 after the hard mask open process, as depicted in FIG. 2A. There is also a gap or bias between the assumed via CD 205 and the actual via CD 207, as depicted in FIG. 2B. Consequently, the actual overlap of the connecting via 207 and the actual trench 203 as depicted by the line 209 is much less than the assumed overlap of the assumed via 205 and the assumed trench 201 as depicted by the line 211.
A need therefore exists for methodology enabling bias compensation to maximize the connection area between metal and connecting via layers.